ESD (electrostatic discharge) protection is commonly applied to circuits to protect circuit elements from damage in case of an ESD event on a control terminal of the circuit element. For instance, in CMOS circuits the use of so-called grounded gate nMOS (ggNMOS) transistors coupled between the control terminal of the circuit element to be protected and ground are commonly used for such ESD protection. The ggNMOS transistor is typically implemented with a relatively large width to length (W/L) ratio, in which gate, source and base are tied to ground, thereby forming a parasitic bipolar (junction) transistor in which the drain is acting as the collector, the gate/source combination acts as the emitter and the substrate acts as the base. Alternatively, in case of a ggNMOS made in a P-well, the P-well acts as the base.
Upon the occurrence of an ESD event on the input signal line, the collector-base junction of the parasitic NPN bipolar transistor becomes reverse biased to the point of avalanche breakdown, at which point the positive current flowing from the base to the ground induces a voltage to appear across the base-emitter junction, which causes the ggNMOS transistor to enter snapback mode until the energy of the ESD event has been depleted.
A drawback of this approach is that its behavior is asymmetrical, i.e. (intentional) negative voltages occurring on the control terminal of the ggnMOS force this device into a conductive state. This is for instance relevant for RF-LDMOS (laterally diffused metal oxide semiconductor) transistors used in power amplifiers. As these amplifiers may be operated as class AB or class C amplifiers, the RF voltage swing can drive the gate voltage below a certain threshold, e.g. −0.7 V, causing a current to flow through the ESD protection. This can cause problems in a bias circuit connected to the LDMOS transistor.
In addition, in some application domains, such as industrial, scientific and medical applications, there is a requirement to be able to switch the LDMOS to a non-conducting state using a negative DC gate bias. In such a case the RF signal may still exist at the gate but the applied bias ensures that the transistor remains in a switched off state, i.e. is no longer amplifying.
The above requirements may be met using dual-sided ESD protection. For instance, US 2007/0228475 discloses a drain-source junction isolated ESD transistor connected in series with an isolation diode element between the gate control line and ground. The isolation diode element prevents a forward biasing of the drain-source junction of the ESD transistor at a −Vgs condition of the transistor device to be protected. Similarly, US 2008/0093624 discloses a back-to-back diode arrangement to provide such dual-sided ESD protection. However, these solutions are unsatisfactory where silicon real estate is at a premium as for such ESD protection circuits typically have a modest current density such that they must cover a relatively large area to be able to sufficiently cope with ESD events. A further drawback of such relatively area intensive solutions is that they increase the capacitance of the ESD circuit, which is also undesirable.